(1) Field of the Invention
The invention relates to the field of design and manufacture of semiconductor integrated circuit devices and more particularly to a novel method for improving the profile of the edge of a step or abrupt feature of the circuit, with respect to coverage by an overlying coating or layer, while also enabling the reduction of the minimum separation design ground rules for circuit feature placement and spacing.
(2) Description of the Prior Art
In the design and manufacture of semiconductor integrated circuit devices, it is necessary to fabricate structural features in the various layers of material involved which have abrupt edges and step-like characteristics. The profiles and aspect ratios of such steps are of significance with respect to coverage by overlying coatings, particularly when the relative dimensions of the step height and overlying coating thickness are closely similar or comparable, as is usually the case. The consequences of this situation are illustrated by reference to FIG. 1, which is a schematic diagram of the cross-section of a portion of a typical semiconductor integrated circuit. In FIG. 1, a semiconductor substrate 10 is coated with an insulating layer of material such as silicon oxide 12. A layer of conductive material 14 is overlaid with another insulating layer 16 through which via contact holes 18 are etched to allow electrical contact with subsequent upper layers 20 as desired. Two significant factors characterize the general suitability of such a typical device cross-section: the detailed nature of the profile of the edge of the via contact hole 21, and the separation between adjacent device features 22, which in this case are the via contact holes. It is readily apparent that the thickness of the layer 20 which crosses over the step 21 will determine the relative ease with which the step 21 can be covered so as to insure the integrity of the portion of layer 20 which is at the sharpest region of the edge. To the extent that the profile of the edge can be controlled so as to vary the acuity of the edge and its relative slope with respect to the vertical, the ease of coverage and the closeness of spacing of adjacent via contact holes will also thus be determined. The same general reasoning applies to other types of edge features common to integrated circuit design and fabrication, such as oxide sidewall profiles adjacent to gate oxide regions, the edges of insulating layers between conductive lines which cross one another, the edges of resistive films, and other similar situations.
The control of edge profiles has been accomplished by taking advantage of such properties of materials such as their etch rates and uniformity of etching under various conditions. Thus, it is possible to etch via contact holes in insulating layers so that the resulting edges are not vertical but have a positive slope or angle less than 90.degree.. This is discussed by Berglund et al in U.S. Pat. No. 4,902,377, in which an isotropic etching process of the oxide insulating layer etches sideways or laterally as well as vertically so that the upper portions of the insulating layer, which are in contact with etching solution longest, have the greatest lateral etching degree, and the result is a tapered edge profile. This will result, of course, in a top dimension considerably larger than the bottom dimension of the contact hole, which must be taken into account in allowing minimum spacing design ground rules for laying out the locations of contact holes in the circuit design. That is, the minimum design spacing must incorporate the fact that the actual etched via holes are larger at the top than the dimensions of the design incorporated in the photomask pattern. Another widely-used method of insuring sloped or tapered edge profiles is to employ either multiple materials with differential rates of etching in a given etchant, as in U.S. Pat. No. 4,888,087 by Moslehi, or different etch methods or etchants in sequence, as discussed by Liu et al in U.S. Pat. No. 5,180,689. None of these references nor the literature in general discuss the use of modifications of the same basic material deposited sequentially in conjunction with differential etching processes to provide an non-vertical step or edge profile while requiring only a minimal increase in the design ground rules for separation between adjacent features to accommodate a larger uppermost dimension of the feature. The employment of a sequential etching process with first an isotropic etch to cause a degree of lateral etching followed by an anisotropic etch to complete the opening of the feature is not mentioned in any reference.